Differences between revisions 1 and 9 (spanning 8 versions)

International IEEE Symposium on Field-Programmable Custom Computing Machines

Best Papers

2010	Rapid RNA Folding: Analysis and Acceleration of the Zuker Recurrence	IEEE Xplore link
2010	Hardware Acceleration of Approximate Tandem Repeat Detection	IEEE Xplore link
2011	Multilevel Granularity Parallelism Synthesis on FPGAs	IEEE Xplore link
2012	Hardware Acceleration of Short Read Mapping	IEEE Xplore link
2013	Parallel Computation of Skyline Queries	IEEE Xplore link
2014	Speeding Up FPGA Placement: Parallel Algorithms and Methods	IEEE Xplore link
2015	Using Dynamic Signal-Tracing to Debug Compiler-Optimized HLS Circuits on FPGAs	IEEE Xplore link
2016 (long)	KAPow: A System Identification Approach to Online Per-module Power Estimation in FPGA Designs
2016 (short)	GRVI Phalanx: A Massively Parallel RISC-V FPGA Accelerator Accelerator
2017 (long)	High-Performance Hardware Merge Sorter
2017 (short)	Evaluating Rapid Application Development with Python for Heterogeneous Processor-based FPGAs

Audience choice for best presentation

2011

HMFlow: Accelerating FPGA Compilation with Hard Macros for Rapid Prototyping

IEEE Xplore link

To date, only awarded in 2011.

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-    ||2010|| ||
    ||2011||Multilevel Granularity Parallelism Synthesis on FPGAs||
    ||2012||Hardware Acceleration of Short Read Mapping||
    ||2013||Parallel Computation of Skyline Queries||
+    ||2010||Rapid RNA Folding: Analysis and Acceleration of the Zuker Recurrence||[[http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=5474066|IEEE Xplore link]]||
    ||2010||Hardware Acceleration of Approximate Tandem Repeat Detection||[[http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=5474065|IEEE Xplore link]]||
    ||2011||Multilevel Granularity Parallelism Synthesis on FPGAs||[[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=5771270|IEEE Xplore link]]||
    ||2012||Hardware Acceleration of Short Read Mapping||[[http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=6239809|IEEE Xplore link]]||
    ||2013||Parallel Computation of Skyline Queries||[[http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=6545986|IEEE Xplore link]]||
    ||2014||Speeding Up FPGA Placement: Parallel Algorithms and Methods||[[http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=6861622|IEEE Xplore link]]||
    ||2015||Using Dynamic Signal-Tracing to Debug Compiler-Optimized HLS Circuits on FPGAs||[[http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=7160056|IEEE Xplore link]]||
    ||2016 (long)||KAPow: A System Identification Approach to Online Per-module Power Estimation in FPGA Designs ||  ||
    ||2016 (short)||GRVI Phalanx: A Massively Parallel RISC-V FPGA Accelerator Accelerator||  ||
    ||2017 (long)||High-Performance Hardware Merge Sorter||  ||
    ||2017 (short)||Evaluating Rapid Application Development with Python for Heterogeneous Processor-based FPGAs|| ||
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-    ||2011||HMFlow: Accelerating FPGA Compilation with Hard Macros for   Rapid Prototyping||
+    ||2011||HMFlow: Accelerating FPGA Compilation with Hard Macros for   Rapid Prototyping||[[http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=5771262|IEEE Xplore link]]||