1698
Comment: typo on linko
|
3009
add 2021 winners
|
Deletions are marked like this. | Additions are marked like this. |
Line 12: | Line 12: |
||2016 (long)||KAPow: A System Identification Approach to Online Per-module Power Estimation in FPGA Designs || || ||2016 (short)||GRVI Phalanx: A Massively Parallel RISC-V FPGA Accelerator Accelerator|| || |
||2016 (long)||KAPow: A System Identification Approach to Online Per-module Power Estimation in FPGA Designs ||[[https://ieeexplore.ieee.org/document/7544748/|IEEE Xplore link]]|| ||2016 (short)||GRVI Phalanx: A Massively Parallel RISC-V FPGA Accelerator Accelerator||[[https://ieeexplore.ieee.org/document/7544735/|IEEE Xplore link]]|| ||2017 (long)||High-Performance Hardware Merge Sorter||[[https://ieeexplore.ieee.org/document/7966636/|IEEE Xplore link]]|| ||2017 (short)||Evaluating Rapid Application Development with Python for Heterogeneous Processor-based FPGAs||[[https://ieeexplore.ieee.org/document/7966663/|IEEE Xplore link]]|| ||2018 (long)||ReBNet: Residual Binarized Neural Network ||[[https://ieeexplore.ieee.org/document/8457633|IEEE Xplore link]]|| ||2018 (short)||Fast and Accurate Estimation of Quality of Results in High-Level Synthesis with Machine Learning||[[https://ieeexplore.ieee.org/document/8457644|IEEE Xplore link]]|| ||2019 (long)||Templatised soft floating-point for High-Level Synthesis|| || ||2019 (short)||Yosys+nextpnr: an Open Source Framework from Verilog to Bitstream for Commercial FPGAs|| || ||2020 (long)||Comparison of Arithmetic Number Formats for Inference in Sum-Product Networks on FPGAs|| || ||2021 (long)||Clockwork: Resource-Efficient Static Scheduling for Multi-Rate Image Processing Applications on FPGAs|| || ||2021 (short)||ESCA: Event-Based Split-CNN Architecture with Data-Level Parallelism on UltraScale+ FPGA|| || |
International IEEE Symposium on Field-Programmable Custom Computing Machines
Best Papers
2010
Rapid RNA Folding: Analysis and Acceleration of the Zuker Recurrence
2010
Hardware Acceleration of Approximate Tandem Repeat Detection
2011
Multilevel Granularity Parallelism Synthesis on FPGAs
2012
Hardware Acceleration of Short Read Mapping
2013
Parallel Computation of Skyline Queries
2014
Speeding Up FPGA Placement: Parallel Algorithms and Methods
2015
Using Dynamic Signal-Tracing to Debug Compiler-Optimized HLS Circuits on FPGAs
2016 (long)
KAPow: A System Identification Approach to Online Per-module Power Estimation in FPGA Designs
2016 (short)
GRVI Phalanx: A Massively Parallel RISC-V FPGA Accelerator Accelerator
2017 (long)
High-Performance Hardware Merge Sorter
2017 (short)
Evaluating Rapid Application Development with Python for Heterogeneous Processor-based FPGAs
2018 (long)
ReBNet: Residual Binarized Neural Network
2018 (short)
Fast and Accurate Estimation of Quality of Results in High-Level Synthesis with Machine Learning
2019 (long)
Templatised soft floating-point for High-Level Synthesis
2019 (short)
Yosys+nextpnr: an Open Source Framework from Verilog to Bitstream for Commercial FPGAs
2020 (long)
Comparison of Arithmetic Number Formats for Inference in Sum-Product Networks on FPGAs
2021 (long)
Clockwork: Resource-Efficient Static Scheduling for Multi-Rate Image Processing Applications on FPGAs
2021 (short)
ESCA: Event-Based Split-CNN Architecture with Data-Level Parallelism on UltraScale+ FPGA
Audience choice for best presentation
- To date, only awarded in 2011.
2011
HMFlow: Accelerating FPGA Compilation with Hard Macros for Rapid Prototyping