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| These are slides from talks given at the 2012 ISFPGA Conference. | These are slides from talks given at the 2012 [[http://www.isfpga.org|ISFPGA Conference]]. |
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| * A Mixed Precision Monte Carlo Methodology for Reconfigurable Accelerator Systems * Intra-Masking Dual-Rail Memory on LUT Implementation for Tamper Resistant AES on FPGA * Compiling Brainiac network processors from C * Octavo: an FPGA-Centric Processor Family * A cycle-accurate, cycle-reproducible multi-FPGA system for accelerating multi-core processor simulation * Reducing the Cost of Floating-Point Mantissa Alignment and Normalization in FPGAs * Rethinking FPGAs: Elude LUT Flexibility Excess with And-Inverter Cones * Limit Study of Energy & Delay Benefits of Component-Specific Routing * Securing Netlist-Level FPGA Design through Exploiting Process Variation and Degradation * CONNECT: Re-Examining Conventional Wisdom for Designing NoCs in the Context of FPGAs * Saturating the Transceiver Bandwidth: Switch Fabric Design on FPGAs |
* [[attachment:140.pdf|A Mixed Precision Monte Carlo Methodology for Reconfigurable Accelerator Systems]] * [[attachment:146.pdf|Intra-Masking Dual-Rail Memory on LUT Implementation for Tamper Resistant AES on FPGA]] * [[attachment:153.pdf|Compiling High Throughput Network Processors]] * [[attachment:157.pdf|Octavo: an FPGA-Centric Processor Family]] * [[attachment:158.pdf|A cycle-accurate, cycle-reproducible multi-FPGA system for accelerating multi-core processor simulation]] * [[attachment:159.pdf|Reducing the Cost of Floating-Point Mantissa Alignment and Normalization in FPGAs]] * [[attachment:169.pdf|Rethinking FPGAs: Elude LUT Flexibility Excess with And-Inverter Cones]] ('''Best Paper''') * [[attachment:174.pdf|Limit Study of Energy & Delay Benefits of Component-Specific Routing]] * [[attachment:178.pdf|Securing Netlist-Level FPGA Design through Exploiting Process Variation and Degradation]] * [[attachment:181.pdf|CONNECT: Re-Examining Conventional Wisdom for Designing NoCs in the Context of FPGAs]] * [[attachment:187.pdf|Saturating the Transceiver Bandwidth: Switch Fabric Design on FPGAs]] |
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| For full papers, see the ACM Digital Library. (''TODO add link'') | For full papers, see the ACM Digital Library [[http://dl.acm.org/citation.cfm?id=2145694&CFID=104851910&CFTOKEN=45296310|page for FPGA2012]]. |
2012 International Symposium on Field-Programmable Gate Arrays
Talk Slides
These are slides from talks given at the 2012 ISFPGA Conference.
Speedy FPGA-Based Packet Classifiers with Low On-Chip Memory Requirements
Easing Multiple FPGA Design with Latency Insensitive Bounded Dataflow Networks
The VTR Project: Architecture and CAD for FPGAs from Verilog to Routing
Optimizing SDRAM Bandwidth for Custom FPGA Loop Accelerators
A coarse-grained stream architecture for cryo-electron microscopy images 3D reconstruction
A Performance and Energy Comparison of FPGAs, GPUs, and Multicores for Sliding-Window Applications
A Configurable Architecture to Limit Wakeup Current in Dynamically-Controlled Power-Gated FPGAs
A Mixed Precision Monte Carlo Methodology for Reconfigurable Accelerator Systems
Intra-Masking Dual-Rail Memory on LUT Implementation for Tamper Resistant AES on FPGA
Reducing the Cost of Floating-Point Mantissa Alignment and Normalization in FPGAs
Rethinking FPGAs: Elude LUT Flexibility Excess with And-Inverter Cones (Best Paper)
Limit Study of Energy & Delay Benefits of Component-Specific Routing
Securing Netlist-Level FPGA Design through Exploiting Process Variation and Degradation
CONNECT: Re-Examining Conventional Wisdom for Designing NoCs in the Context of FPGAs
Saturating the Transceiver Bandwidth: Switch Fabric Design on FPGAs
Papers
For full papers, see the ACM Digital Library page for FPGA2012.