|
Size: 2115
Comment:
|
Size: 2115
Comment: updating name
|
| Deletions are marked like this. | Additions are marked like this. |
| Line 18: | Line 18: |
| * [[attachment:153.pdf|Compiling Brainiac network processors from C]] | * [[attachment:153.pdf|Compiling High Throughput Network Processors]] |
2012 International Symposium on Field-Programmable Gate Arrays
Talk Slides
These are slides from talks given at the 2012 ISFPGA Conference.
Speedy FPGA-Based Packet Classifiers with Low On-Chip Memory Requirements
Easing Multiple FPGA Design with Latency Insensitive Bounded Dataflow Networks
The VTR Project: Architecture and CAD for FPGAs from Verilog to Routing
Optimizing SDRAM Bandwidth for Custom FPGA Loop Accelerators
A coarse-grained stream architecture for cryo-electron microscopy images 3D reconstruction
A Performance and Energy Comparison of FPGAs, GPUs, and Multicores for Sliding-Window Applications
A Configurable Architecture to Limit Wakeup Current in Dynamically-Controlled Power-Gated FPGAs
A Mixed Precision Monte Carlo Methodology for Reconfigurable Accelerator Systems
Intra-Masking Dual-Rail Memory on LUT Implementation for Tamper Resistant AES on FPGA
- A cycle-accurate, cycle-reproducible multi-FPGA system for accelerating multi-core processor simulation
- Reducing the Cost of Floating-Point Mantissa Alignment and Normalization in FPGAs
- Rethinking FPGAs: Elude LUT Flexibility Excess with And-Inverter Cones
Limit Study of Energy & Delay Benefits of Component-Specific Routing
- Securing Netlist-Level FPGA Design through Exploiting Process Variation and Degradation
CONNECT: Re-Examining Conventional Wisdom for Designing NoCs in the Context of FPGAs
- Saturating the Transceiver Bandwidth: Switch Fabric Design on FPGAs
Papers
For full papers, see the ACM Digital Library. (TODO add link)