= 2012 International Symposium on Field-Programmable Gate Arrays =

== Talk Slides ==

These are slides from talks given at the 2012 [[http://www.isfpga.org|ISFPGA Conference]].

 * [[attachment:102.pdf|Speedy FPGA-Based Packet Classifiers with Low On-Chip Memory Requirements]]
 * [[attachment:104.pdf|Multi-Ported Memories for FPGAs via XOR]]
 * [[attachment:113.pdf|Easing Multiple FPGA Design with Latency Insensitive Bounded Dataflow Networks]]
 * [[attachment:124.pdf|The VTR Project: Architecture and CAD for FPGAs from Verilog to Routing]]
 * [[attachment:125.pdf|A Scalable Approach for Automated Precision Analysis]]
 * [[attachment:126.pdf|Optimizing SDRAM Bandwidth for Custom FPGA Loop Accelerators]]
 * [[attachment:127.pdf|A coarse-grained stream architecture for cryo-electron microscopy images 3D reconstruction]]
 * [[attachment:130.pdf|A Performance and Energy Comparison of FPGAs, GPUs, and Multicores for Sliding-Window Applications]]
 * [[attachment:133.pdf|A Configurable Architecture to Limit Wakeup Current in Dynamically-Controlled Power-Gated FPGAs]]
 * [[attachment:140.pdf|A Mixed Precision Monte Carlo Methodology for Reconfigurable Accelerator Systems]]
 * [[attachment:146.pdf|Intra-Masking Dual-Rail Memory on LUT Implementation for Tamper Resistant AES on FPGA]]
 * [[attachment:153.pdf|Compiling High Throughput Network Processors]]
 * [[attachment:157.pdf|Octavo: an FPGA-Centric Processor Family]]
 * [[attachment:158.pdf|A cycle-accurate, cycle-reproducible multi-FPGA system for accelerating multi-core processor simulation]]
 * [[attachment:159.pdf|Reducing the Cost of Floating-Point Mantissa Alignment and Normalization in FPGAs]]
 * [[attachment:169.pdf|Rethinking FPGAs: Elude LUT Flexibility Excess with And-Inverter Cones]] ('''Best Paper''')
 * [[attachment:174.pdf|Limit Study of Energy & Delay Benefits of Component-Specific Routing]]
 * [[attachment:178.pdf|Securing Netlist-Level FPGA Design through Exploiting Process Variation and Degradation]]
 * [[attachment:181.pdf|CONNECT: Re-Examining Conventional Wisdom for Designing NoCs in the Context of FPGAs]]
 * [[attachment:187.pdf|Saturating the Transceiver Bandwidth: Switch Fabric Design on FPGAs]]

== Papers ==
   
  For full papers, see the ACM Digital Library [[http://dl.acm.org/citation.cfm?id=2145694&CFID=104851910&CFTOKEN=45296310|page for FPGA2012]].