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* [[attachment:p1.pdf|Improving high level synthesis optimization opportunity through polyhedral transformations]] * [[attachment:p1.pdf|Towards simulator-like observability for FPGAs: a virtual overlay network for trace-buffers]] * [[attachment:p1.pdf|Polyhedral-based data reuse optimization for configurable computing]] * [[attachment:p1.pdf|Accelerating ncRNA homology search with FPGAs]] * [[attachment:p1.pdf|Accelerating subsequence similarity search based on dynamic time warping distance with FPGA]] * [[attachment:p1.pdf|Video-rate stereo matching using markov random field TRW-S inference on a hybrid CPU+FPGA computing platform]] * [[attachment:p1.pdf|Fully-functional FPGA prototype with fine-grain programmable body biasing]] * [[attachment:p1.pdf|GROK-LAB: generating real on-chip knowledge for intra-cluster delays using timing extraction]] * [[attachment:p1.pdf|Side-channel attacks on the bitstream encryption mechanism of Altera Stratix II: facilitating black-box analysis using software reverse-engineering]] * [[attachment:p1.pdf|Sensing nanosecond-scale voltage attacks and natural transients in FPGAs]] * [[attachment:p1.pdf|Word-length optimization beyond straight line code]] * [[attachment:p1.pdf|Placement of repair circuits for in-field FPGA repair]] * [[attachment:p1.pdf|Heracles: a tool for fast RTL-based design space exploration of multicore processors]] * [[attachment:p1.pdf|Location, location, location: the role of spatial locality in asymptotic energy minimization]] * [[attachment:p1.pdf|Architectural enhancements in Stratix V™]] * [[attachment:p1.pdf|Minimum energy operation for clustered island-style FPGAs]] * [[attachment:p1.pdf|Improving bitstream compression by modifying FPGA architecture]] * [[attachment:p1.pdf|Elastic CGRAs]] * [[attachment:p1.pdf|Embedding-based placement of processing element networks on FPGAs for physical model simulation]] * [[attachment:p1.pdf|Area-efficient near-associative memories on FPGAs]] * [[attachment:p1.pdf|Dynafuse: dynamic dependence analysis for FPGA pipeline fusion and locality optimizations]] * [[attachment:p1.pdf|A remote memory access infrastructure for global address space programming models in FPGAs]] * [[attachment:p1.pdf|C-to-CoRAM: compiling perfect loop nests to the portable CoRAM abstraction]] * [[attachment:p1.pdf|Architecture support for custom instructions with memory operations]] * [[attachment:p1.pdf|An FPGA based parallel architecture for music melody matching]] * [[attachment:p1.pdf|An FPGA memcached appliance]] * [[attachment:p1.pdf|High throughput and programmable online trafficclassifier on FPGA]] |
* [[attachment:p1.pdf|Improving high level synthesis optimization opportunity through polyhedral transformations]] * [[attachment:p1.pdf|Towards simulator-like observability for FPGAs: a virtual overlay network for trace-buffers]] * [[attachment:p1.pdf|Polyhedral-based data reuse optimization for configurable computing]] * [[attachment:p1.pdf|Accelerating ncRNA homology search with FPGAs]] * [[attachment:p1.pdf|Accelerating subsequence similarity search based on dynamic time warping distance with FPGA]] * [[attachment:p1.pdf|Video-rate stereo matching using markov random field TRW-S inference on a hybrid CPU+FPGA computing platform]] * [[attachment:p1.pdf|Fully-functional FPGA prototype with fine-grain programmable body biasing]] * [[attachment:p1.pdf|GROK-LAB: generating real on-chip knowledge for intra-cluster delays using timing extraction]] * [[attachment:p1.pdf|Side-channel attacks on the bitstream encryption mechanism of Altera Stratix II: facilitating black-box analysis using software reverse-engineering]] * [[attachment:p1.pdf|Sensing nanosecond-scale voltage attacks and natural transients in FPGAs]] * [[attachment:p1.pdf|Word-length optimization beyond straight line code]] * [[attachment:p1.pdf|Placement of repair circuits for in-field FPGA repair]] * [[attachment:p1.pdf|Heracles: a tool for fast RTL-based design space exploration of multicore processors]] * [[attachment:p1.pdf|Location, location, location: the role of spatial locality in asymptotic energy minimization]] * [[attachment:p1.pdf|Architectural enhancements in Stratix V™]] * [[attachment:p1.pdf|Minimum energy operation for clustered island-style FPGAs]] * [[attachment:p1.pdf|Improving bitstream compression by modifying FPGA architecture]] * [[attachment:p1.pdf|Elastic CGRAs]] * [[attachment:p1.pdf|Embedding-based placement of processing element networks on FPGAs for physical model simulation]] * [[attachment:p1.pdf|Area-efficient near-associative memories on FPGAs]] * [[attachment:p1.pdf|Dynafuse: dynamic dependence analysis for FPGA pipeline fusion and locality optimizations]] * [[attachment:p1.pdf|A remote memory access infrastructure for global address space programming models in FPGAs]] * [[attachment:p1.pdf|C-to-CoRAM: compiling perfect loop nests to the portable CoRAM abstraction]] * [[attachment:p1.pdf|Architecture support for custom instructions with memory operations]] * [[attachment:p1.pdf|An FPGA based parallel architecture for music melody matching]] * [[attachment:p1.pdf|An FPGA memcached appliance]] * [[attachment:p1.pdf|High throughput and programmable online trafficclassifier on FPGA]] |
2013 International Symposium on Field-Programmable Gate Arrays
Talk Slides
These are slides from talks given at the 2013 ISFPGA Conference.
Improving high level synthesis optimization opportunity through polyhedral transformations
Towards simulator-like observability for FPGAs: a virtual overlay network for trace-buffers
Polyhedral-based data reuse optimization for configurable computing
Accelerating subsequence similarity search based on dynamic time warping distance with FPGA
Fully-functional FPGA prototype with fine-grain programmable body biasing
GROK-LAB: generating real on-chip knowledge for intra-cluster delays using timing extraction
Sensing nanosecond-scale voltage attacks and natural transients in FPGAs
Heracles: a tool for fast RTL-based design space exploration of multicore processors
Location, location, location: the role of spatial locality in asymptotic energy minimization
Improving bitstream compression by modifying FPGA architecture
Embedding-based placement of processing element networks on FPGAs for physical model simulation
Dynafuse: dynamic dependence analysis for FPGA pipeline fusion and locality optimizations
A remote memory access infrastructure for global address space programming models in FPGAs
C-to-CoRAM: compiling perfect loop nests to the portable CoRAM abstraction
Architecture support for custom instructions with memory operations
An FPGA based parallel architecture for music melody matching
High throughput and programmable online trafficclassifier on FPGA
Papers
For full papers, see the ACM Digital Library page for FPGA2013.