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| * [[attachment:p1.pdf|Fully-functional FPGA prototype with fine-grain programmable body biasing]] * [[attachment:p1.pdf|GROK-LAB: generating real on-chip knowledge for intra-cluster delays using timing extraction]] * [[attachment:p1.pdf|Side-channel attacks on the bitstream encryption mechanism of Altera Stratix II: facilitating black-box analysis using software reverse-engineering]] * [[attachment:p1.pdf|Sensing nanosecond-scale voltage attacks and natural transients in FPGAs]] |
* [[attachment:p73.pdf|Fully-functional FPGA prototype with fine-grain programmable body biasing]] * [[attachment:p81.pdf|GROK-LAB: generating real on-chip knowledge for intra-cluster delays using timing extraction]] * [[attachment:p91.pdf|Side-channel attacks on the bitstream encryption mechanism of Altera Stratix II: facilitating black-box analysis using software reverse-engineering]] * [[attachment:p101.pptx|Sensing nanosecond-scale voltage attacks and natural transients in FPGAs]] |
2013 International Symposium on Field-Programmable Gate Arrays
Talk Slides
These are slides from talks given at the 2013 ISFPGA Conference.
Improving high level synthesis optimization opportunity through polyhedral transformations
Towards simulator-like observability for FPGAs: a virtual overlay network for trace-buffers
Polyhedral-based data reuse optimization for configurable computing (Best Paper)
Accelerating subsequence similarity search based on dynamic time warping distance with FPGA
Fully-functional FPGA prototype with fine-grain programmable body biasing
GROK-LAB: generating real on-chip knowledge for intra-cluster delays using timing extraction
Sensing nanosecond-scale voltage attacks and natural transients in FPGAs
Heracles: a tool for fast RTL-based design space exploration of multicore processors
Location, location, location: the role of spatial locality in asymptotic energy minimization
Improving bitstream compression by modifying FPGA architecture
Embedding-based placement of processing element networks on FPGAs for physical model simulation
Dynafuse: dynamic dependence analysis for FPGA pipeline fusion and locality optimizations
A remote memory access infrastructure for global address space programming models in FPGAs
C-to-CoRAM: compiling perfect loop nests to the portable CoRAM abstraction
Architecture support for custom instructions with memory operations
An FPGA based parallel architecture for music melody matching
High throughput and programmable online trafficclassifier on FPGA
Papers
For full papers, see the ACM Digital Library page for FPGA2013.