2014 International Symposium on Field-Programmable Gate Arrays

Talk Slides

These are slides from talks given at the 2014 ISFPGA Conference.

• Fast and Effective Placement and Routing Directed High-Level Synthesis for FPGAs

• Optimizing Effective Interconnect Capacitance for FPGA Power Reduction (Best Paper)

• Towards Interconnect-Adaptive Packing for FPGAs

• Rent’s Rule Based FPGA Packing for Routability Optimization

• Modular Multi-ported SRAM-based Memories

• Revisiting And-Inverter Cones

• Scalable Multi-Access Flash Store for Big Data Analytics

• Dynamic Voltage & Frequency Scaling with Online Slack Measurement

• CAD and Routing Architecture for Interposer-Based Multi-FPGA Systems

• Memory Block Based Scan-BIST Architecture for Application-Dependent FPGA Testing

• FPGA-based Biophysically-Meaningful Modeling of Olivocerebellar Neurons
• Square-Rich Fixed Point Polynomial Evaluation on FPGAs

• Soft Vector Processors with Streaming Pipelines

• MORP: Makespan Optimization for Processors with an Embedded Reconfigurable Fabric

• OmpSs@Zynq All-Programmable SoC Ecosystem

• A FPGA Prototype Design Emphasis on Low Power Technique

• Hardware Acceleration of Database Operations
• A Scalable Sparse Matrix-Vector Multiplication Kernel For Energy-Efficient Sparse-BLAS On FPGAs
• Binary Stochastic Implementation of Digital Logic
• Accelerating Parameter Estimation for Multivariate Self-Exciting Point Processes
• Energy-Efficient Multiplier-Less Discrete Convolver through Probabilistic Domain Transformation

• Wordwidth, Instructions, Looping, and Virtualization: The Role of Sharing in Absolute Energy Minimization

• Theory and Algorithm for Generalized Memory Partitioning in High-Level Synthesis

• Using High-level Synthesis and Formal Analysis to Predict and Preempt Attacks on Industrial Control Systems

• MPack: Global Memory Optimization for Stream Applications in High-Level Synthesis

• A soft error vulnerability analysis framework for Xilinx FPGAs

• A Power-Side-Channel Based Digital to Analog Converter for Xilinx FPGAs
• Accelerating Frequent Item Counting with FPGA

• Combining Computation with Communication Optimizations in System Synthesis for Streaming Applications

• Quantifying the Cost and Benefit of Latency Insensitive Communication on FPGAs