1500
Comment: sessions 4 and 5
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1894
session 6
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* Hardware Acceleration of Database Operations * A Scalable Sparse Matrix-Vector Multiplication Kernel For Energy-Efficient Sparse-BLAS On FPGAs * Binary Stochastic Implementation of Digital Logic * Accelerating Parameter Estimation for Multivariate Self-Exciting Point Processes * Energy-Efficient Multiplier-Less Discrete Convolver through Probabilistic Domain Transformation |
2014 International Symposium on Field-Programmable Gate Arrays
Talk Slides
These are slides from talks given at the 2014 ISFPGA Conference.
Fast and Effective Placement and Routing Directed High-Level Synthesis for FPGAs
Optimizing Effective Interconnect Capacitance for FPGA Power Reduction
- Modular Multi-ported SRAM-based Memories
- Revisiting And-Inverter Cones
Dynamic Voltage & Frequency Scaling with Online Slack Measurement
CAD and Routing Architecture for Interposer-Based Multi-FPGA Systems
Memory Block Based Scan-BIST Architecture for Application-Dependent FPGA Testing
- FPGA-based Biophysically-Meaningful Modeling of Olivocerebellar Neurons
- Square-Rich Fixed Point Polynomial Evaluation on FPGAs
- MORP: Makespan Optimization for Processors with an Embedded Reconfigurable Fabric
- A FPGA Prototype Design Emphasis on Low Power Technique
- Hardware Acceleration of Database Operations
- A Scalable Sparse Matrix-Vector Multiplication Kernel For Energy-Efficient Sparse-BLAS On FPGAs
- Binary Stochastic Implementation of Digital Logic
- Accelerating Parameter Estimation for Multivariate Self-Exciting Point Processes
- Energy-Efficient Multiplier-Less Discrete Convolver through Probabilistic Domain Transformation