= 2014 International Symposium on Field-Programmable Gate Arrays =

== Talk Slides ==

These are slides from talks given at the 2014 [[http://www.isfpga.org|ISFPGA Conference]].

  * [[attachment:session1_1.pptx|Fast and Effective Placement and Routing Directed High-Level Synthesis for FPGAs]]
  * [[attachment:session1_2.ppt|Optimizing Effective Interconnect Capacitance for FPGA Power Reduction]] ('''Best Paper''')
  * [[attachment:session1_3.pptx|Towards Interconnect-Adaptive Packing for FPGAs]]
  * [[attachment:session1_4.pdf|Rent’s Rule Based FPGA Packing for Routability Optimization]]
  * [[attachment:session2_1.pdf|Modular Multi-ported SRAM-based Memories]]
  * Revisiting And-Inverter Cones
  * [[attachment:session2_3.pptx|Scalable Multi-Access Flash Store for Big Data Analytics]]
  * Dynamic Voltage & Frequency Scaling with Online Slack Measurement
  * [[attachment:session3_2.pdf|CAD and Routing Architecture for Interposer-Based Multi-FPGA Systems]]
  * [[attachment:session3_3.pdf|Memory Block Based Scan-BIST Architecture for Application-Dependent FPGA Testing]]
  * FPGA-based Biophysically-Meaningful Modeling of Olivocerebellar Neurons
  * Square-Rich Fixed Point Polynomial Evaluation on FPGAs
  * [[attachment:session5_1.pptx|Soft Vector Processors with Streaming Pipelines]]
  * MORP: Makespan Optimization for Processors with an Embedded Reconfigurable Fabric
  * [[attachment:session5_3.pdf|OmpSs@Zynq All-Programmable SoC Ecosystem]]
  * [[attachment:session5_4.pptx|A FPGA Prototype Design Emphasis on Low Power Technique]]
  * Hardware Acceleration of Database Operations
  * A Scalable Sparse Matrix-Vector Multiplication Kernel For Energy-Efficient Sparse-BLAS On FPGAs
  * Binary Stochastic Implementation of Digital Logic
  * Accelerating Parameter Estimation for Multivariate Self-Exciting Point Processes 
  * Energy-Efficient Multiplier-Less Discrete Convolver through Probabilistic Domain Transformation
  * [[attachment:session7_1.pptx|Wordwidth, Instructions, Looping, and Virtualization: The Role of Sharing in Absolute Energy Minimization]]
  * Theory and Algorithm for Generalized Memory Partitioning in High-Level Synthesis
  * [[attachment:session7_3.pdf|Using High-level Synthesis and Formal Analysis to Predict and Preempt Attacks on Industrial Control Systems]]
  * [[attachment:session7_4.pdf|MPack: Global Memory Optimization for  Stream Applications in High-Level Synthesis]]
  * [[attachment:session7_5.pptx|A soft error vulnerability analysis framework for Xilinx FPGAs]]
  * A Power-Side-Channel Based Digital to Analog Converter for Xilinx FPGAs
  * Accelerating Frequent Item Counting with FPGA
  * [[attachment:session8_1.pptx|Combining Computation with Communication Optimizations in System Synthesis for Streaming Applications]]
  * [[attachment:session8_2.pdf|Quantifying the Cost and Benefit of Latency Insensitive Communication on FPGAs]]