Differences between revisions 9 and 10

International Symposium on Field-Programmable Gate Arrays

Best Papers

2011	CoRAM: an in-fabric memory architecture for FPGA-based computing	ACM DL Link
2012	Rethinking FPGAs: elude the flexibility excess of LUTs with and-inverter cones	ACM DL Link
2013	Polyhedral-Based Data Reuse Optimization for Configurable Computing	ACM DL Link
2014	Optimizing Effective Interconnect Capacitance for FPGA Power Reduction	ACM DL Link
2015	Take the Highway: Design for Embedded NoCs on FPGAs	ACM DL Link
2016	FPRESSO: Enabling Express Transistor-Level Exploration of FPGA Architectures	ACM DL Link
2017	ESE: Efficient Speech Recognition Engine with Compressed LSTM on FPGA	ACM DL Link
2018	FASTCF: FPGA-based Accelerator for Stochastic-Gradient-Descent-based Collaborative Filtering	ACM DL Link
2019	HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Reconfigurable Computing
2020	Buffer Placement and Sizing for High-Performance Dataflow Circuits	ACM DL Link

-  ⇤ ← Revision 9 as of 2020-02-27 19:48:15 → 
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  Editor: AndreDeHon
  Comment: add 2020 best paper
+   ← Revision 10 as of 2020-02-27 19:48:31 → ⇥
  Size: 1478
  Editor: AndreDeHon
  Comment: fix format
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-||2020||Buffer Placement and Sizing for High-Performance Dataflow Circuits||[[https://dl.acm.org/doi/abs/10.1145/3373087.3375314ACM DL Link]]||
+||2020||Buffer Placement and Sizing for High-Performance Dataflow Circuits||[[https://dl.acm.org/doi/abs/10.1145/3373087.3375314|ACM DL Link]]||