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| * Is High Level Synthesis Ready for Business? A Computational Finance Case Study<<BR>>Gordon Inggs, Shane Fleming, David Thomas and Wayne Luk | * [[attachment:s112_inggs.pdf|Is High Level Synthesis Ready for Business? A Computational Finance Case Study]]<<BR>>Gordon Inggs, Shane Fleming, David Thomas and Wayne Luk |
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| * Comparing Performance, Productivity and Scalability of the TILT Overlay Processor to OpenCL HLS<<BR>>Rafat Rashid, J. Gregory Steffan and Vaughn Betz | * [[attachment:s113_rashid.pdf|Comparing Performance, Productivity and Scalability of the TILT Overlay Processor to OpenCL HLS]]<<BR>>Rafat Rashid, J. Gregory Steffan and Vaughn Betz |
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| * Analyzing the Impact of Heterogeneous Blocks on FPGA Placement Quality<<BR>>Chang Xu, Wentai Zhang and Guojie Luo | * [[attachment:s115_luo.pdf|Analyzing the Impact of Heterogeneous Blocks on FPGA Placement Quality]]<<BR>>Chang Xu, Wentai Zhang and Guojie Luo |
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| * Low-latency Option Pricing using Systolic Binomial Trees '''(Best Paper Candidate)'''<<BR>>Aryan Tavakkoli and David B. Thomas | * [[attachment:s121_tavakkoli.pdf|Low-latency Option Pricing using Systolic Binomial Trees]] '''(Best Paper Candidate)'''<<BR>>Aryan Tavakkoli and David B. Thomas |
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| * Time Sharing of Runtime Coarse-Grain Reconfigurable Architectures Processing Elements in Multi-Process Systems<<BR>>Benjamin Carrion Schafer | * [[attachment:s131_shafer.pdf|Time Sharing of Runtime Coarse-Grain Reconfigurable Architectures Processing Elements in Multi-Process Systems]]<<BR>>Benjamin Carrion Schafer |
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| * Architectural Synthesis of Computational Pipelines with Decoupled Memory Access<<BR>>Shaoyi Cheng and John Wawrzynek | * [[attachment:s132_cheng.pdf|Architectural Synthesis of Computational Pipelines with Decoupled Memory Access]]<<BR>>Shaoyi Cheng and John Wawrzynek |
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| * Improve Memory Access for Achieving Both Performance and Energy Efficiencies on Heterogeneous Systems<<BR>>Hongyuan Ding and Miaoqing Huang | * [[attachment:s133_ding.pdf|Improve Memory Access for Achieving Both Performance and Energy Efficiencies on Heterogeneous Systems]]<<BR>>Hongyuan Ding and Miaoqing Huang |
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| * Approaching Overhead-Free Execution on FPGA Soft-Processors<<BR>>Charles Eric LaForest, Jason Anderson and J. Gregory Steffan | * [[attachment:s134_laforest.pdf|Approaching Overhead-Free Execution on FPGA Soft-Processors]]<<BR>>Charles Eric LaForest, Jason Anderson and J. Gregory Steffan |
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| * An Efficient FPGA Implementation of QR Decomposition using a Novel Systolic Array Architecture based on Enhanced Vectoring CORDIC<<BR>>Jianfeng Zhang, Paul Chow and Hengzhu Liu | * [[attachment:s213_zhang.pdf|An Efficient FPGA Implementation of QR Decomposition using a Novel Systolic Array Architecture based on Enhanced Vectoring CORDIC]]<<BR>>Jianfeng Zhang, Paul Chow and Hengzhu Liu |
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| * A Universal FPGA-based Floating-point Matrix Processor for Mobile Systems<<BR>>Wenqiang Wang, Kaiyuan Guo, Mengyuan Gu, Yuchun Ma and Yu Wang | * [[attachment:s215_guo.pdf|A Universal FPGA-based Floating-point Matrix Processor for Mobile Systems]]<<BR>>Wenqiang Wang, Kaiyuan Guo, Mengyuan Gu, Yuchun Ma and Yu Wang |
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| * ROTORouter: Router Support for Endpoint-Authorized Decentralized Traffic Filtering to Prevent DoS Attacks<<BR>>Albert Kwon, Kaiyu Zhang, Perk Lun Lim, Yuchen Pan, Jonathan M. Smith and André DeHon | * [[attachment:s311_kwon.pdf|ROTORouter: Router Support for Endpoint-Authorized Decentralized Traffic Filtering to Prevent DoS Attacks]]<<BR>>Albert Kwon, Kaiyu Zhang, Perk Lun Lim, Yuchen Pan, Jonathan M. Smith and André DeHon |
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| * Parallel Resampling for Particle Filters on FPGAs<<BR>>Shuanglong Liu, Grigorios Mingas and Christos-Savvas Bouganis | * [[attachment:s312_liu.pdf|Parallel Resampling for Particle Filters on FPGAs]]<<BR>>Shuanglong Liu, Grigorios Mingas and Christos-Savvas Bouganis |
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| * Evaluation of SNMP-like protocol to manage a NoC Emulation Platform<<BR>>Otávio Alcântara de Lima Junior, Virginie Fresse and Frédéric Rousseau | * [[attachment:s313_fresse.pdf|Evaluation of SNMP-like protocol to manage a NoC Emulation Platform]]<<BR>>Otávio Alcântara de Lima Junior, Virginie Fresse and Frédéric Rousseau |
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| * A High-Performance Low-Power Near-Vt RRAM-based FPGA '''(Best Paper Candidate)'''<<BR>>Xifan Tang, Pierre-Emmanuel Gaillardon and Giovanni De Micheli | * [[attachment:s314_tang.pdf|A High-Performance Low-Power Near-Vt RRAM-based FPGA]] '''(Best Paper Candidate)'''<<BR>>Xifan Tang, Pierre-Emmanuel Gaillardon and Giovanni De Micheli |
2014 International Conference on Field Programmable Technologies (FPT 2014)
Talk Slides
Below are slides from the oral presentations at FPT 2014
1.1 Tools & Design Productivity
Design Re-Use for Compile Time Reduction in FPGA High-Level Synthesis Flows (Best Paper Award)
Marcel Gort and Jason AndersonIs High Level Synthesis Ready for Business? A Computational Finance Case Study
Gordon Inggs, Shane Fleming, David Thomas and Wayne LukComparing Performance, Productivity and Scalability of the TILT Overlay Processor to OpenCL HLS
Rafat Rashid, J. Gregory Steffan and Vaughn BetzSize Aware Placement for Island Style FPGAs
Junying Huang, Colin Yu Lin, Yang Liu, Zhihua Li and Haigang YangAnalyzing the Impact of Heterogeneous Blocks on FPGA Placement Quality
Chang Xu, Wentai Zhang and Guojie Luo
1.2 Financial Applications
Low-latency Option Pricing using Systolic Binomial Trees (Best Paper Candidate)
Aryan Tavakkoli and David B. ThomasCollaborative Processing of Least-Square Monte Carlo for American Options
Jinzhe Yang, Ce Guo, Wayne Luk and Terence NaharAccelerating Transfer Entropy Computation
Shengjia Shao, Ce Guo, Wayne Luk and Stephen WestonFPGA-accelerated Monte-Carlo Integration using Stratified Sampling and Brownian Bridges
Mark de Jong, Vlad-Mihai Sima, Koen Bertels and David Thomas
1.3 Architecture & Runtime Systems
Time Sharing of Runtime Coarse-Grain Reconfigurable Architectures Processing Elements in Multi-Process Systems
Benjamin Carrion SchaferArchitectural Synthesis of Computational Pipelines with Decoupled Memory Access
Shaoyi Cheng and John WawrzynekImprove Memory Access for Achieving Both Performance and Energy Efficiencies on Heterogeneous Systems
Hongyuan Ding and Miaoqing HuangApproaching Overhead-Free Execution on FPGA Soft-Processors
Charles Eric LaForest, Jason Anderson and J. Gregory Steffan
2.1 Mathematical Circuits
Low-Latency Double-Precision Floating-Point Division for FPGAs
Björn Liebig and Andreas KochEfficient FPGA Implementation of Digit Parallel Online Arithmetic Operators (Best Paper Candidate)
Kan Shi, David Boland and George A. ConstantinidesAn Efficient FPGA Implementation of QR Decomposition using a Novel Systolic Array Architecture based on Enhanced Vectoring CORDIC
Jianfeng Zhang, Paul Chow and Hengzhu LiuArea Efficient Floating Point Adder and Multiplier with IEEE-754 Compatible Semantics
Andreas EhliarA Universal FPGA-based Floating-point Matrix Processor for Mobile Systems
Wenqiang Wang, Kaiyuan Guo, Mengyuan Gu, Yuchun Ma and Yu Wang
3.1 Applications & Devices
ROTORouter: Router Support for Endpoint-Authorized Decentralized Traffic Filtering to Prevent DoS Attacks
Albert Kwon, Kaiyu Zhang, Perk Lun Lim, Yuchen Pan, Jonathan M. Smith and André DeHonParallel Resampling for Particle Filters on FPGAs
Shuanglong Liu, Grigorios Mingas and Christos-Savvas BouganisEvaluation of SNMP-like protocol to manage a NoC Emulation Platform
Otávio Alcântara de Lima Junior, Virginie Fresse and Frédéric RousseauA High-Performance Low-Power Near-Vt RRAM-based FPGA (Best Paper Candidate)
Xifan Tang, Pierre-Emmanuel Gaillardon and Giovanni De MicheliA Pure-CMOS Nonvolatile Multi-Context Configuration Memory for Dynamically Reconfigurable FPGAs
Kosuke Tatsumura, Masato Oda and Shinichi Yasuda