2014 International Conference on Field Programmable Technologies (FPT 2014)

Talk Slides

Below are slides from the oral presentations at FPT 2014

1.1 Tools & Design Productivity

• Design Re-Use for Compile Time Reduction in FPGA High-Level Synthesis Flows (Best Paper Award)
  Marcel Gort and Jason Anderson

• Is High Level Synthesis Ready for Business? A Computational Finance Case Study
  Gordon Inggs, Shane Fleming, David Thomas and Wayne Luk

• Comparing Performance, Productivity and Scalability of the TILT Overlay Processor to OpenCL HLS
  Rafat Rashid, J. Gregory Steffan and Vaughn Betz

• Size Aware Placement for Island Style FPGAs
  Junying Huang, Colin Yu Lin, Yang Liu, Zhihua Li and Haigang Yang

• Analyzing the Impact of Heterogeneous Blocks on FPGA Placement Quality
  Chang Xu, Wentai Zhang and Guojie Luo

1.2 Financial Applications

• Low-latency Option Pricing using Systolic Binomial Trees (Best Paper Candidate)
  Aryan Tavakkoli and David B. Thomas

• Collaborative Processing of Least-Square Monte Carlo for American Options
  Jinzhe Yang, Ce Guo, Wayne Luk and Terence Nahar

• Accelerating Transfer Entropy Computation
  Shengjia Shao, Ce Guo, Wayne Luk and Stephen Weston

• FPGA-accelerated Monte-Carlo Integration using Stratified Sampling and Brownian Bridges
  Mark de Jong, Vlad-Mihai Sima, Koen Bertels and David Thomas

1.3 Architecture & Runtime Systems

• Time Sharing of Runtime Coarse-Grain Reconfigurable Architectures Processing Elements in Multi-Process Systems
  Benjamin Carrion Schafer

• Architectural Synthesis of Computational Pipelines with Decoupled Memory Access
  Shaoyi Cheng and John Wawrzynek

• Improve Memory Access for Achieving Both Performance and Energy Efficiencies on Heterogeneous Systems
  Hongyuan Ding and Miaoqing Huang

• Approaching Overhead-Free Execution on FPGA Soft-Processors
  Charles Eric LaForest, Jason Anderson and J. Gregory Steffan

2.1 Mathematical Circuits

• Low-Latency Double-Precision Floating-Point Division for FPGAs
  Björn Liebig and Andreas Koch

• Efficient FPGA Implementation of Digit Parallel Online Arithmetic Operators (Best Paper Candidate)
  Kan Shi, David Boland and George A. Constantinides

• An Efficient FPGA Implementation of QR Decomposition using a Novel Systolic Array Architecture based on Enhanced Vectoring CORDIC
  Jianfeng Zhang, Paul Chow and Hengzhu Liu

• Area Efficient Floating Point Adder and Multiplier with IEEE-754 Compatible Semantics
  Andreas Ehliar

• A Universal FPGA-based Floating-point Matrix Processor for Mobile Systems
  Wenqiang Wang, Kaiyuan Guo, Mengyuan Gu, Yuchun Ma and Yu Wang

3.1 Applications & Devices

• ROTORouter: Router Support for Endpoint-Authorized Decentralized Traffic Filtering to Prevent DoS Attacks
  Albert Kwon, Kaiyu Zhang, Perk Lun Lim, Yuchen Pan, Jonathan M. Smith and André DeHon

• Parallel Resampling for Particle Filters on FPGAs
  Shuanglong Liu, Grigorios Mingas and Christos-Savvas Bouganis

• Evaluation of SNMP-like protocol to manage a NoC Emulation Platform
  Otávio Alcântara de Lima Junior, Virginie Fresse and Frédéric Rousseau

• A High-Performance Low-Power Near-Vt RRAM-based FPGA (Best Paper Candidate)
  Xifan Tang, Pierre-Emmanuel Gaillardon and Giovanni De Micheli

• A Pure-CMOS Nonvolatile Multi-Context Configuration Memory for Dynamically Reconfigurable FPGAs
  Kosuke Tatsumura, Masato Oda and Shinichi Yasuda