= 2014 International Conference on Field Programmable Technologies (FPT 2014) =

== Talk Slides ==

Below are slides from the oral presentations at FPT 2014

=== 1.1 Tools & Design Productivity ===

 * Design Re-Use for Compile Time Reduction in FPGA High-Level Synthesis Flows '''(Best Paper Award)'''<<BR>>Marcel Gort and Jason Anderson

 * [[attachment:s112_inggs.pdf|Is High Level Synthesis Ready for Business? A Computational Finance Case Study]]<<BR>>Gordon Inggs, Shane Fleming, David Thomas and Wayne Luk

 * [[attachment:s113_rashid.pdf|Comparing Performance, Productivity and Scalability of the TILT Overlay Processor to OpenCL HLS]]<<BR>>Rafat Rashid, J. Gregory Steffan and Vaughn Betz

 * Size Aware Placement for Island Style FPGAs<<BR>>Junying Huang, Colin Yu Lin, Yang Liu, Zhihua Li and Haigang Yang

 * [[attachment:s115_luo.pdf|Analyzing the Impact of Heterogeneous Blocks on FPGA Placement Quality]]<<BR>>Chang Xu, Wentai Zhang and Guojie Luo

=== 1.2 Financial Applications ===

 * [[attachment:s121_tavakkoli.pdf|Low-latency Option Pricing using Systolic Binomial Trees]] '''(Best Paper Candidate)'''<<BR>>Aryan Tavakkoli and David B. Thomas

 * Collaborative Processing of Least-Square Monte Carlo for American Options<<BR>>Jinzhe Yang, Ce Guo, Wayne Luk and Terence Nahar

 * Accelerating Transfer Entropy Computation<<BR>>Shengjia Shao, Ce Guo, Wayne Luk and Stephen Weston

 * FPGA-accelerated Monte-Carlo Integration using Stratified Sampling and Brownian Bridges<<BR>>Mark de Jong, Vlad-Mihai Sima, Koen Bertels and David Thomas

=== 1.3 Architecture & Runtime Systems ===

 * [[attachment:s131_shafer.pdf|Time Sharing of Runtime Coarse-Grain Reconfigurable Architectures Processing Elements in Multi-Process Systems]]<<BR>>Benjamin Carrion Schafer

 * [[attachment:s132_cheng.pdf|Architectural Synthesis of Computational Pipelines with Decoupled Memory Access]]<<BR>>Shaoyi Cheng and John Wawrzynek

 * [[attachment:s133_ding.pdf|Improve Memory Access for Achieving Both Performance and Energy Efficiencies on Heterogeneous Systems]]<<BR>>Hongyuan Ding and Miaoqing Huang

 * [[attachment:s134_laforest.pdf|Approaching Overhead-Free Execution on FPGA Soft-Processors]]<<BR>>Charles Eric LaForest, Jason Anderson and J. Gregory Steffan 

=== 2.1 Mathematical Circuits ===

 * Low-Latency Double-Precision Floating-Point Division for FPGAs<<BR>>Björn Liebig and Andreas Koch

 * [[attachment:s212_shi.pdf|Efficient FPGA Implementation of Digit Parallel Online Arithmetic Operators]] '''(Best Paper Candidate)'''<<BR>>Kan Shi, David Boland and George A. Constantinides

 * [[attachment:s213_zhang.pdf|An Efficient FPGA Implementation of QR Decomposition using a Novel Systolic Array Architecture based on Enhanced Vectoring CORDIC]]<<BR>>Jianfeng Zhang, Paul Chow and Hengzhu Liu

 * Area Efficient Floating Point Adder and Multiplier with IEEE-754 Compatible Semantics<<BR>>Andreas Ehliar

 * [[attachment:s215_guo.pdf|A Universal FPGA-based Floating-point Matrix Processor for Mobile Systems]]<<BR>>Wenqiang Wang, Kaiyuan Guo, Mengyuan Gu, Yuchun Ma and Yu Wang 

=== 3.1 Applications & Devices ===
 * [[attachment:s311_kwon.pdf|ROTORouter: Router Support for Endpoint-Authorized Decentralized Traffic Filtering to Prevent DoS Attacks]]<<BR>>Albert Kwon, Kaiyu Zhang, Perk Lun Lim, Yuchen Pan, Jonathan M. Smith and André DeHon

 * [[attachment:s312_liu.pdf|Parallel Resampling for Particle Filters on FPGAs]]<<BR>>Shuanglong Liu, Grigorios Mingas and Christos-Savvas Bouganis

 * [[attachment:s313_fresse.pdf|Evaluation of SNMP-like protocol to manage a NoC Emulation Platform]]<<BR>>Otávio Alcântara de Lima Junior, Virginie Fresse and Frédéric Rousseau

 * [[attachment:s314_tang.pdf|A High-Performance Low-Power Near-Vt RRAM-based FPGA]] '''(Best Paper Candidate)'''<<BR>>Xifan Tang, Pierre-Emmanuel Gaillardon and Giovanni De Micheli

 * A Pure-CMOS Nonvolatile Multi-Context Configuration Memory for Dynamically Reconfigurable FPGAs<<BR>>Kosuke Tatsumura, Masato Oda and Shinichi Yasuda