Andrew Ensor Technologies for the Square Kilometre Array project
Andre DeHon Understanding and Exploiting the Energy advantages of Field-Programmable Technologies
Vaughn Betz The Case for Embedding Networks-on-Chip in FPGA Architectures
Improved Carry Chain Mapping for the VTR Flow
A Co-Design Approach for Accelerated SQL Query Processing via FPGA-based Data Filtering
Leftmost Longest Regular Expression Matching in Reconfigurable Logic
Packet Processing with a NoC-Enhanced FPGA
Resource and Memory Management Techniques for the High-Level Synthesis of Software Threads into Parallel FPGA Hardware
Exploring Pipe Implementations using an OpenCL Framework for FPGAs
Energy Minimization in the Time-Space Continuum
Analyzing the Divide between FPGA Academic and Commercial Results
A Fully Pipelined Kernel Normalised Least Mean Squares Processor For Accelerated Parameter Optimisation
Using Round-Robin Tracepoints to Debug Multithreaded HLS Circuits on FPGAs
Provably Correct Development of Reconfigurable Hardware Designs via Equational Reasoning
Accerated Cell Imaging and Classification on FPGAs for Quantitative-phase Asymmetric-detection Time-stretch Optical Microscopy
QuickDough:A Rapid FPGA Loop Accelerator Design Framework Using Soft CGRA Overlay
OpenCL Library of Stream Memory Components Targeting FPGAs
Braiding: a Scheme for Resolving Hazards in NORMA
An FPGA-based Real-time Simultaneous Localization and Mapping System
HETRIS: Adaptive Floorplanning for Heterogeneous FPGAs
Automatic FPGA System and Interconnect Construction with Multicast and Customizable Topology
An Exact MCMC Accelerator Under Custom Precision
Hardware Design of a Fast, Parallel Random Tree Path Planner
Behavioral-Level IP Integration in High-Level Synthesis
JIT Trace-based Verification in High-Level Synthesis
An Adaptive Cross-Layer Fault Recovery Solution for Reconfigurable SoCs
Custom-Sized Caches in Application-Specific Memory Hierarchies
A Self-aware Data Compression System on FPGA in Hadoop
FPGA Implementation of Low-Power and High-PSNR DCT/IDCT Architecture based on Adaptive Recoding CORDIC