Reviewer 1 ---------- This paper evaluates the power consumption of time-multiplexed architectures, presents way to optimize the power, and compares it to a spatial architecture. While this may be mostly of academic interest now, the experiments are well-done, and there is there is value in quantifying what might already have been common wisdom. The most interesting part of the paper is the discussion related to Figure 4, however, I found that figure difficult to understand; in particular, it is almost impossible to deduce what each architectural variant looks like (the colors of the blocks and borders are confusing). I realize space is at a premium in the paper, but it would be really helpful to draw each variant a bit more clearly. It is never stated, but from the discussion in II-b.2, I assume that a low power LSTP process is used. It would be important to state this. In all cases, the diffeq benchmarks stood out as having higher power ratios than the other benchmarks. I wasn�t clear on why this is. The circuits do have lower p, but other circuits have low p too. I appreciated the Sensitivity section. The title seems a bit broad. Energy minimization here really only applies to the TM architecture. Reviewer 2 ---------- This paper explores the energy consumption of spatial vs. time-multiplexed FPGAs. It is a very good question to ask, and the authors do an enormous amount of work in the exploring the answer. Further, they’ve found a legitimate way to put ‘time-space continuum’ into a paper title, which is an achievement all by itself! Comparisons of this kind are very difficult to make, and yet the paper, which is very well written, covers a huge amount of detail in trying to answer the question. My principal issue with the paper is that it is dense and terse enough that some things are not explained well, but still I can’t see that there is much room to provide that explanation. The paper is generally very well written, and easy to read. It begins with a careful description of where energy is consumed in an FPGA, and how they have set about modeling it. It is a little disappointing that the underlying routing architecture that they have chosen to model is a hierarchical tree-based one, which has never been shown to have any sustainable advantage over more flat architectures, and certainly has some serious disadvantages (hard boundaries for one; inappropriate length wires for another). I’d ask that the authors at least make a comment as to the major differences between flat, island style, segmented routing architectures and the one they have chosen. That said, the result and exploration is very interesting. A big part of the paper is the attempts to minimize the energy-consuming parts of a time-multiplexed FPGA, and some good work is done here. The final result, that spatial is likely to use less energy, is definitely worth knowing. Hopefully this will hold with a flat, island style segmented architecture? Reviewer 3 ---------- The paper presents a study of the energy requirements for fixed versus time-multiplexed FPGA fabrics, and comes to the conclusion that the time-multiplixed fabrics have a significant energy disadvantage. The topic is interesting, and the authors have put a lot of work into trying to develop an end to end toolchain. Attempting to quantify the hypothesised advantages of time-multiplexed FPGAs is a useful contribution to the debate. A criticism is that the paper is very low on details, and it would be exceptionally difficult to recreate the results from the information in the paper. There appears to be no commitment to open-source the tool-chain or results, so it is unclear that whether other researcher would be able to use or critique the arguments properly. Compounding this is the poor structure of the paper, and a tendency to race through and skip over details. This feels like a journal paper that has been cut down to fit into 8 pages, and it would benefit from loses some sections at the end and concentrating on explaining the main results. The paper also assumes that the reader knows the details of the paper before reading, and often refers to things that haven't been explained, or assumes the reader will have the same assumptions about implementation that the authors do. Even some quite basic things were not made clear, such as the run-time of circuits and the relative clock rates. How much of the energy increase is due to one circuit being on for longer? - Personally I found the title a little whimsical. It doesn't really indicate what the paper is going to be about. The introduction doesn't explain what a time multiplexed FPGA is, it more launches into a lis of what people have done. It then ends with some sentences about what "we" did, which reads a bit like contributions, though they are then listed later. It tries to pack too much in too quickly. "Most of the energy in FPGAs goes into switching long wires [4]." - This is quite a sweeping claim, and it's not clear that one paper about 90nm technology from 2007 is really sufficient justification. (It may be well be true, I'm just saying [4] does not support the argument well). I think the intro section could be restructured a bit to have a more logical order. At the moment it spends a lot of time recapping what the paper does in multiple ways, and doesn't give as much context to the contributions as it could. "multiplixed" [sic] "Wire energy is the dominant energy component in spatial FPGA designs [4]." - It seems even more dubious to be relying on one paper for this key modulling assumption at this point. Are there no other examples of other people saying the same thing (ideally more recently)? Again: I do not disagree, but you should support the assertion better. A lot of the stuff in the background appears to be work being done by the authors, but I would expect it to be more about what other people have done and basic fundamental knowledge that is needed to understand and qualify the paper. "Instruction Memory: Since instruction memories are accessed sequentially," - At this point the reader doesn't know exactly what you mean by instruction memories, or why they are access sequentially. Presumably your time-multiplexed FPGA can only iterate through configurations in a fixed order? That would seem to be a design-choice, at least in my understanding of time multiplexing. There are no units on the x-axis of figure 1. It's really not clear how to interpet the information presented and discussed in figure 1. The meaning of imem and dmem in this paper has not been explained yet. The reader can only guess, and may well be wrong. Part II.A assumes a lot on the part of the reader. Possibly it will be explained in more detail later on, but at this point I only have a vague understanding of the multicontext approach being taken here. Figures 2 and 3 could be better labelled, particularly figure 3. partitoner [sic] configruation [sic] "we explored a series of optimizations that successively separated the LUT" - These seems like important details, but it is not clear what exact the modifications are. What does the sparse input PE look like? I think we're supposed to extract that from figure 4, but I find it difficult to follow (compounded by trying to read it in black-and-white initially). For instance, what is the blue triangle in the bottom left? Again, the next activity approach seems like an important and possibly subtle detail, but it is despatched in one paragraph. It's not clear how things like clocks are handled. Some notion of clock rate and execution time should be discussed. Is the assumption that both designs are at the same clock rate? Is the energy increase because it runs for higher wall-clock time to do the same calculation? Section VIII seemed to be loading too much in. It would be better to simplify the paper a bit, and use the space to better explain the earlier parts. Reviewer 4 ---------- The paper provides a useful assessment of whether energy savings are possible from time multiplexed FPGAs instead of regular FPGAs. The authors gloss over the circuit assumptions behind their analysis and more details that could be signficiant for the assessnment. While it may not substantially impact the conclusions, the description of the logic energy design is unclear. It seems to imply a usage of pass transistors without level restorers which is unlikely to ever be used. This calls into question some of the numbers. As well is not clear if the power analysis results are based on gate-level simulations with timing. If not the impact of glitching might be under-estimated which could significantly influence the activity factors depending on the logic and its implementation. Reviewer 5 ---------- This paper presents an impressive and complete study of the power of time-domain multiplexed FPGAs vs. conventional spatial FPGAs. The methodology is very thorough as the authors built a complete CAD flow and detailed circuitry and models to perform the evaluation. It is also very clearly written. This paper addresses a long standing question more thoroughly than any prior work, making a great contribution to the literature. The writing quality is generally very good, with a few sections that get somewhat dense. In Section III.B, please explain what you mean by "the 4-LUT depth of the critical path serves as a lower bound on the number of waves". Does this mean your architecture cannot cascade two LUTs together in a single clock cycle / wave? Please expand on this point. Please define p precisely. From the context one can infer that p is the rent exponent of the application but I don't believe it is formally defined. It found Fig. 5 took some time to understand. Bolding or thickening the main routing wires (00, 01 etc.) might help make the figure easier to understand. Section VII: Why are wires reduced by a factor of 32 for the S=8 case? Please explain the derivation of this number. The rightmost plot in Figure 10 has many vertically-small bars. The figure would be easier to understand if some of the very small power contributors were grouped into an "other" category to simplify the color legend.