Attachment 'review_1.txt'
Download 1 Reviewer 1
2 ----------
3 This paper evaluates the power consumption of time-multiplexed architectures, presents way to optimize the power, and compares it to a spatial architecture. While this may be mostly of academic interest now, the experiments are well-done, and there is there is value in quantifying what might already have been common wisdom.
4
5 The most interesting part of the paper is the discussion related to Figure 4, however, I found that figure difficult to understand; in particular, it is almost impossible to deduce what each architectural variant looks like (the colors of the blocks and borders are confusing). I realize space is at a premium in the paper, but it would be really helpful to draw each variant a bit more clearly.
6
7 It is never stated, but from the discussion in II-b.2, I assume that a low power LSTP process is used. It would be important to state this.
8
9 In all cases, the diffeq benchmarks stood out as having higher power ratios than the other benchmarks. I wasn�t clear on why this is. The circuits do have lower p, but other circuits have low p too.
10
11 I appreciated the Sensitivity section.
12
13 The title seems a bit broad. Energy minimization here really only applies to the TM architecture.
14
15 Reviewer 2
16 ----------
17 This paper explores the energy consumption of spatial vs. time-multiplexed FPGAs. It is a very good question to ask, and the authors do an enormous amount of work in the exploring the answer. Further, they’ve found a legitimate way to put ‘time-space continuum’ into a paper title, which is an achievement all by itself!
18
19 Comparisons of this kind are very difficult to make, and yet the paper, which is very well written, covers a huge amount of detail in trying to answer the question. My principal issue with the paper is that it is dense and terse enough that some things are not explained well, but still I can’t see that there is much room to provide that explanation.
20
21 The paper is generally very well written, and easy to read. It begins with a careful description of where energy is consumed in an FPGA, and how they have set about modeling it.
22
23 It is a little disappointing that the underlying routing architecture that they have chosen to model is a hierarchical tree-based one, which has never been shown to have any sustainable advantage over more flat architectures, and certainly has some serious disadvantages (hard boundaries for one; inappropriate length wires for another). I’d ask that the authors at least make a comment as to the major differences between flat, island style, segmented routing architectures and the one they have chosen.
24
25 That said, the result and exploration is very interesting. A big part of the paper is the attempts to minimize the energy-consuming parts of a time-multiplexed FPGA, and some good work is done here.
26
27 The final result, that spatial is likely to use less energy, is definitely worth knowing. Hopefully this will hold with a flat, island style segmented architecture?
28
29 Reviewer 3
30 ----------
31
32 The paper presents a study of the energy requirements
33 for fixed versus time-multiplexed FPGA fabrics, and
34 comes to the conclusion that the time-multiplixed
35 fabrics have a significant energy disadvantage.
36
37 The topic is interesting, and the authors have put
38 a lot of work into trying to develop an end to end
39 toolchain. Attempting to quantify the hypothesised
40 advantages of time-multiplexed FPGAs is a useful
41 contribution to the debate.
42
43 A criticism is that the paper is very low on
44 details, and it would be exceptionally difficult
45 to recreate the results from the information in
46 the paper. There appears to be no commitment to
47 open-source the tool-chain or results, so it is
48 unclear that whether other researcher would be
49 able to use or critique the arguments properly.
50
51 Compounding this is the poor structure of the
52 paper, and a tendency to race through and skip
53 over details. This feels like a journal paper that
54 has been cut down to fit into 8 pages, and it
55 would benefit from loses some sections at the
56 end and concentrating on explaining the main
57 results. The paper also assumes that the reader
58 knows the details of the paper before reading,
59 and often refers to things that haven't been
60 explained, or assumes the reader will have the
61 same assumptions about implementation that the
62 authors do.
63
64 Even some quite basic things were not made
65 clear, such as the run-time of circuits and
66 the relative clock rates. How much of the
67 energy increase is due to one circuit being
68 on for longer?
69
70 -
71
72 Personally I found the title a little whimsical. It doesn't
73 really indicate what the paper is going to be about.
74
75 The introduction doesn't explain what a time
76 multiplexed FPGA is, it more launches into a
77 lis of what people have done. It then ends with
78 some sentences about what "we" did, which
79 reads a bit like contributions, though they
80 are then listed later. It tries to pack too
81 much in too quickly.
82
83 "Most of the energy in FPGAs goes into switching long wires
84 [4]."
85 -
86 This is quite a sweeping claim, and it's not clear
87 that one paper about 90nm technology from 2007
88 is really sufficient justification. (It may be well
89 be true, I'm just saying [4] does not support the
90 argument well).
91
92 I think the intro section could be restructured
93 a bit to have a more logical order. At the moment
94 it spends a lot of time recapping what the paper
95 does in multiple ways, and doesn't give as much
96 context to the contributions as it could.
97
98 "multiplixed" [sic]
99
100 "Wire energy is the dominant energy component
101 in spatial FPGA designs [4]."
102 -
103 It seems even more dubious to be relying on
104 one paper for this key modulling assumption
105 at this point. Are there no other examples of
106 other people saying the same thing (ideally
107 more recently)? Again: I do not disagree, but
108 you should support the assertion better.
109
110 A lot of the stuff in the background appears
111 to be work being done by the authors, but I
112 would expect it to be more about what other
113 people have done and basic fundamental
114 knowledge that is needed to understand and
115 qualify the paper.
116
117 "Instruction Memory: Since instruction memories are
118 accessed sequentially,"
119 -
120 At this point the reader doesn't know exactly
121 what you mean by instruction memories, or
122 why they are access sequentially. Presumably
123 your time-multiplexed FPGA can only iterate
124 through configurations in a fixed order? That
125 would seem to be a design-choice, at least
126 in my understanding of time multiplexing.
127
128 There are no units on the x-axis of figure 1.
129
130 It's really not clear how to interpet the
131 information presented and discussed in figure 1.
132 The meaning of imem and dmem in this paper has
133 not been explained yet. The reader can only
134 guess, and may well be wrong.
135
136 Part II.A assumes a lot on the part of the reader.
137 Possibly it will be explained in more detail
138 later on, but at this point I only have a vague
139 understanding of the multicontext approach being
140 taken here. Figures 2 and 3 could be better labelled,
141 particularly figure 3.
142
143 partitoner [sic]
144
145 configruation [sic]
146
147 "we explored a series of optimizations that successively
148 separated the LUT"
149 -
150 These seems like important details, but it is not
151 clear what exact the modifications are. What does
152 the sparse input PE look like? I think we're
153 supposed to extract that from figure 4, but
154 I find it difficult to follow (compounded by
155 trying to read it in black-and-white initially).
156 For instance, what is the blue triangle in the
157 bottom left?
158
159 Again, the next activity approach seems like an
160 important and possibly subtle detail, but it is
161 despatched in one paragraph.
162
163 It's not clear how things like clocks are handled.
164 Some notion of clock rate and execution time
165 should be discussed. Is the assumption that both
166 designs are at the same clock rate? Is the energy
167 increase because it runs for higher wall-clock
168 time to do the same calculation?
169
170 Section VIII seemed to be loading too much
171 in. It would be better to simplify the paper
172 a bit, and use the space to better explain
173 the earlier parts.
174
175 Reviewer 4
176 ----------
177 The paper provides a useful assessment of whether energy savings are possible from time multiplexed FPGAs instead of regular FPGAs.
178
179 The authors gloss over the circuit assumptions behind their analysis and more details that could be signficiant for the assessnment. While it may not substantially impact the conclusions, the description of the logic energy design is unclear. It seems to imply a usage of pass transistors without level restorers which is unlikely to ever be used. This calls into question some of the numbers.
180
181 As well is not clear if the power analysis results are based on gate-level simulations with timing. If not the impact of glitching might be under-estimated which could significantly influence the activity factors depending on the logic and its implementation.
182
183 Reviewer 5
184 ----------
185 This paper presents an impressive and complete study of the power of time-domain multiplexed
186 FPGAs vs. conventional spatial FPGAs. The methodology is very thorough as the authors
187 built a complete CAD flow and detailed circuitry and models to perform the
188 evaluation. It is also very clearly written. This paper addresses a long standing
189 question more thoroughly than any prior work, making a great contribution to the literature.
190
191 The writing quality is generally very good, with a few sections that get somewhat dense.
192 In Section III.B, please explain what you mean by "the 4-LUT depth of the critical path serves as
193 a lower bound on the number of waves". Does this mean your architecture cannot cascade two
194 LUTs together in a single clock cycle / wave? Please expand on this point.
195
196 Please define p precisely. From the context one can infer that p is the rent exponent of
197 the application but I don't believe it is formally defined.
198
199 It found Fig. 5 took some time to understand. Bolding or thickening the main routing wires (00, 01 etc.)
200 might help make the figure easier to understand.
201
202 Section VII: Why are wires reduced by a factor of 32 for the S=8 case? Please explain the derivation of
203 this number.
204
205 The rightmost plot in Figure 10 has many vertically-small bars. The figure would be easier to understand if
206 some of the very small power contributors were grouped into an "other" category to simplify the
207 color legend.
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