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== Keynotes == [[attachment:ensor_keynote.pdf|Andrew Ensor, Technologies for the Square Kilometre Array project]]<<BR>> [[attachment:dehon_keynote.pdf|Andre DeHon, Understanding and Exploiting the Energy advantages of Field-Programmable Technologies]]<<BR>> [[attachment:betz_keynote.pptx|Vaughn Betz, The Case for Embedding Networks-on-Chip in FPGA Architectures]]<<BR>> == Papers == |
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| [[attachment:andreas_sql.pdf |A Co-Design Approach for Accelerated SQL Query Processing via FPGA- based Data Filtering]]<<BR>> [[attachment:atasu_leftmost-regex.pdf |Leftmost Longest Regular Expression Matching in Reconfigurable Logi c]]<<BR>> |
[[attachment:andreas_sql.pdf |A Co-Design Approach for Accelerated SQL Query Processing via FPGA-based Data Filtering]]<<BR>> [[attachment:atasu_leftmost-regex.pdf |Leftmost Longest Regular Expression Matching in Reconfigurable Logic]]<<BR>> |
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| [[attachment:choi_hls-threads.pdf |Resource and Memory Management Techniques for the High-Level Synthe sis of Software Threads into Parallel FPGA Hardware]]<<BR>> [[attachment:chow_opencl-pipes.pdf |Exploring Pipe Implementations using an OpenCL Framework for FPGAs] ]<<BR>> |
[[attachment:choi_hls-threads.pdf |Resource and Memory Management Techniques for the High-Level Synthesis of Software Threads into Parallel FPGA Hardware]]<<BR>> [[attachment:chow_opencl-pipes.pdf |Exploring Pipe Implementations using an OpenCL Framework for FPGAs]]<<BR>> |
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| [[attachment:elias_commercial-vs-academic.pdf|Analyzing the Divide between FPGA Academic and Commercial Results]] <<BR>> [[attachment:fraser_knlms.pdf |A Fully Pipelined Kernel Normalised Least Mean Squares Processor Fo r Accelerated Parameter Optimisation]]<<BR>> [[attachment:goeders_debug-hls.pdf |Using Round-Robin Tracepoints to Debug Multithreaded HLS Circuits o n FPGAs]]<<BR>> [[attachment:harrison_eqnreason.pdf |Provably Correct Development of Reconfigurable Hardware Designs via Equational Reasoning]]<<BR>> [[attachment:hayden_cell.pdf |Accerated Cell Imaging and Classification on FPGAs for Quantitative -phase Asymmetric-detection Time-stretch Optical Microscopy]]<<BR>> [[attachment:hayden_quickdough.pdf |QuickDough:A Rapid FPGA Loop Accelerator Design Framework Using Sof t CGRA Overlay]]<<BR>> |
[[attachment:elias_commercial-vs-academic.pdf|Analyzing the Divide between FPGA Academic and Commercial Results]]<<BR>> [[attachment:fraser_knlms.pdf |A Fully Pipelined Kernel Normalised Least Mean Squares Processor For Accelerated Parameter Optimisation]]<<BR>> [[attachment:goeders_debug-hls.pdf |Using Round-Robin Tracepoints to Debug Multithreaded HLS Circuits on FPGAs]]<<BR>> [[attachment:harrison_eqnreason.pdf |Provably Correct Development of Reconfigurable Hardware Designs via Equational Reasoning]]<<BR>> [[attachment:hayden_cell.pdf |Accerated Cell Imaging and Classification on FPGAs for Quantitative-phase Asymmetric-detection Time-stretch Optical Microscopy]]<<BR>> [[attachment:hayden_quickdough.pdf |QuickDough:A Rapid FPGA Loop Accelerator Design Framework Using Soft CGRA Overlay]]<<BR>> |
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| [[attachment:mengyuan_slam.pptx |An FPGA-based Real-time Simultaneous Localization and Mapping Syste m]]<<BR>> |
[[attachment:mengyuan_slam.pptx |An FPGA-based Real-time Simultaneous Localization and Mapping System]]<<BR>> |
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| [[attachment:rodionov_auto-topo.pptx |Automatic FPGA System and Interconnect Construction with Multicast and Customizable Topology]]<<BR>> |
[[attachment:rodionov_auto-topo.pptx |Automatic FPGA System and Interconnect Construction with Multicast and Customizable Topology]]<<BR>> |
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| [[attachment:size_random-tree.pptx |Hardware Design of a Fast, Parallel Random Tree Path Planner]]<<BR> > |
[[attachment:size_random-tree.pptx |Hardware Design of a Fast, Parallel Random Tree Path Planner]]<<BR>> |
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| [[attachment:wang_fault-soc.pdf |An Adaptive Cross-Layer Fault Recovery Solution for Reconfigurable SoCs]]<<BR>> [[attachment:winterstein_custom-cache.pdf |Custom-Sized Caches in Application-Specific Memory Hierarchies]]<<B R>> |
[[attachment:wang_fault-soc.pdf |An Adaptive Cross-Layer Fault Recovery Solution for Reconfigurable SoCs]]<<BR>> [[attachment:winterstein_custom-cache.pdf |Custom-Sized Caches in Application-Specific Memory Hierarchies]]<<BR>> |
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| [[attachment:zhang_cordic.pptx |FPGA Implementation of Low-Power and High-PSNR DCT/IDCT Architectur e based on Adaptive Recoding CORDIC]]<<BR>> |
[[attachment:zhang_cordic.pptx |FPGA Implementation of Low-Power and High-PSNR DCT/IDCT Architecture based on Adaptive Recoding CORDIC]]<<BR>> |
Keynotes
Andrew Ensor, Technologies for the Square Kilometre Array project
Andre DeHon, Understanding and Exploiting the Energy advantages of Field-Programmable Technologies
Vaughn Betz, The Case for Embedding Networks-on-Chip in FPGA Architectures
Papers
Improved Carry Chain Mapping for the VTR Flow
A Co-Design Approach for Accelerated SQL Query Processing via FPGA-based Data Filtering
Leftmost Longest Regular Expression Matching in Reconfigurable Logic
Packet Processing with a NoC-Enhanced FPGA
Resource and Memory Management Techniques for the High-Level Synthesis of Software Threads into Parallel FPGA Hardware
Exploring Pipe Implementations using an OpenCL Framework for FPGAs
Energy Minimization in the Time-Space Continuum
Analyzing the Divide between FPGA Academic and Commercial Results
A Fully Pipelined Kernel Normalised Least Mean Squares Processor For Accelerated Parameter Optimisation
Using Round-Robin Tracepoints to Debug Multithreaded HLS Circuits on FPGAs
Provably Correct Development of Reconfigurable Hardware Designs via Equational Reasoning
Accerated Cell Imaging and Classification on FPGAs for Quantitative-phase Asymmetric-detection Time-stretch Optical Microscopy
QuickDough:A Rapid FPGA Loop Accelerator Design Framework Using Soft CGRA Overlay
OpenCL Library of Stream Memory Components Targeting FPGAs
Braiding: a Scheme for Resolving Hazards in NORMA
An FPGA-based Real-time Simultaneous Localization and Mapping System
HETRIS: Adaptive Floorplanning for Heterogeneous FPGAs
Automatic FPGA System and Interconnect Construction with Multicast and Customizable Topology
An Exact MCMC Accelerator Under Custom Precision
Hardware Design of a Fast, Parallel Random Tree Path Planner
Behavioral-Level IP Integration in High-Level Synthesis
JIT Trace-based Verification in High-Level Synthesis
An Adaptive Cross-Layer Fault Recovery Solution for Reconfigurable SoCs
Custom-Sized Caches in Application-Specific Memory Hierarchies
A Self-aware Data Compression System on FPGA in Hadoop
FPGA Implementation of Low-Power and High-PSNR DCT/IDCT Architecture based on Adaptive Recoding CORDIC