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← Revision 15 as of 2015-12-20 03:01:33 ⇥
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| [[attachment:ensor_keynote.pdf|Andrew Ensor, Technologies for the Square Kilometre Array project]]<br> [[attachment:dehon_keynote.pdf|Andre DeHon, Understanding and Exploiting the Energy advantages of Field-Programmable Technologies]]<br> [[attachment:betz_keynote.pptx|Vaughn Betz, The Case for Embedding Networks-on-Chip in FPGA Architectures]]<br> |
[[attachment:ensor_keynote.pdf|Andrew Ensor, Technologies for the Square Kilometre Array project]]<<BR>> [[attachment:dehon_keynote.pdf|Andre DeHon, Understanding and Exploiting the Energy advantages of Field-Programmable Technologies]]<<BR>> [[attachment:betz_keynote.pptx|Vaughn Betz, The Case for Embedding Networks-on-Chip in FPGA Architectures]]<<BR>> |
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| [Improved Carry Chain Mapping for the VTR Flow](./ana_carry-chain-vtr.pptx) | [A Co-Design Approach for Accelerated SQL Query Processing via FPGA-based Data Filtering](./andreas_sql.pdf) | [Leftmost Longest Regular Expression Matching in Reconfigurable Logic](./atasu_leftmost-regex.pdf) | [Packet Processing with a NoC-Enhanced FPGA](./bitar_pp-noc.pptx) | [Resource and Memory Management Techniques for the High-Level Synthesis of Software Threads into Parallel FPGA Hardware](./choi_hls-threads.pdf) | [Exploring Pipe Implementations using an OpenCL Framework for FPGAs](./chow_opencl-pipes.pdf) | [Energy Minimization in the Time-Space Continuum](./dehon_space-time.pdf) | [Analyzing the Divide between FPGA Academic and Commercial Results](./elias_commercial-vs-academic.pdf) | [A Fully Pipelined Kernel Normalised Least Mean Squares Processor For Accelerated Parameter Optimisation](./fra ser_knlms.pdf) | [Using Round-Robin Tracepoints to Debug Multithreaded HLS Circuits on FPGAs](./goeders_debug-hls.pdf) | [Provably Correct Development of Reconfigurable Hardware Designs via Equational Reasoning](./harrison_eqnreason .pdf) | [Accerated Cell Imaging and Classification on FPGAs for Quantitative-phase Asymmetric-detection Time-stretch Op tical Microscopy](./hayden_cell.pdf) | [QuickDough:A Rapid FPGA Loop Accelerator Design Framework Using Soft CGRA Overlay](./hayden_quickdough.pdf) | [OpenCL Library of Stream Memory Components Targeting FPGAs](./jasmina_opencl-streams.pdf) | [Braiding: a Scheme for Resolving Hazards in NORMA](./leong_braiding.pdf) | [An FPGA-based Real-time Simultaneous Localization and Mapping System](./mengyuan_slam.pptx) | [HETRIS: Adaptive Floorplanning for Heterogeneous FPGAs](./murray_hetris.pdf) | [Automatic FPGA System and Interconnect Construction with Multicast and Customizable Topology](./rodionov_auto- topo.pptx) | [An Exact MCMC Accelerator Under Custom Precision](./shuanglong_mcmc.pdf) | [Hardware Design of a Fast, Parallel Random Tree Path Planner](./size_random-tree.pptx) | [Behavioral-Level IP Integration in High-Level Synthesis](./swathi_behav-hls.pptx) | [JIT Trace-based Verification in High-Level Synthesis](./swathi_jit-trace.pptx) | [An Adaptive Cross-Layer Fault Recovery Solution for Reconfigurable SoCs](./wang_fault-soc.pdf) | [Custom-Sized Caches in Application-Specific Memory Hierarchies](./winterstein_custom-cache.pdf) | [A Self-aware Data Compression System on FPGA in Hadoop](./yubin_hadoop.pptx) | [FPGA Implementation of Low-Power and High-PSNR DCT/IDCT Architecture based on Adaptive Recoding CORDIC](./zhan g_cordic.pptx) |
[[attachment:ana_carry-chain-vtr.pptx |Improved Carry Chain Mapping for the VTR Flow]]<<BR>> [[attachment:andreas_sql.pdf |A Co-Design Approach for Accelerated SQL Query Processing via FPGA-based Data Filtering]]<<BR>> [[attachment:atasu_leftmost-regex.pdf |Leftmost Longest Regular Expression Matching in Reconfigurable Logic]]<<BR>> [[attachment:bitar_pp-noc.pptx |Packet Processing with a NoC-Enhanced FPGA]]<<BR>> [[attachment:choi_hls-threads.pdf |Resource and Memory Management Techniques for the High-Level Synthesis of Software Threads into Parallel FPGA Hardware]]<<BR>> [[attachment:chow_opencl-pipes.pdf |Exploring Pipe Implementations using an OpenCL Framework for FPGAs]]<<BR>> [[attachment:dehon_space-time.pdf |Energy Minimization in the Time-Space Continuum]] ('''best paper''')<<BR>> [[attachment:elias_commercial-vs-academic.pdf|Analyzing the Divide between FPGA Academic and Commercial Results]]<<BR>> [[attachment:fraser_knlms.pdf |A Fully Pipelined Kernel Normalised Least Mean Squares Processor For Accelerated Parameter Optimisation]]<<BR>> [[attachment:goeders_debug-hls.pdf |Using Round-Robin Tracepoints to Debug Multithreaded HLS Circuits on FPGAs]]<<BR>> [[attachment:harrison_eqnreason.pdf |Provably Correct Development of Reconfigurable Hardware Designs via Equational Reasoning]]<<BR>> [[attachment:hayden_cell.pdf |Accerated Cell Imaging and Classification on FPGAs for Quantitative-phase Asymmetric-detection Time-stretch Optical Microscopy]]<<BR>> [[attachment:hayden_quickdough.pdf |QuickDough:A Rapid FPGA Loop Accelerator Design Framework Using Soft CGRA Overlay]]<<BR>> [[attachment:jasmina_opencl-streams.pdf |OpenCL Library of Stream Memory Components Targeting FPGAs]]<<BR>> [[attachment:leong_braiding.pdf |Braiding: a Scheme for Resolving Hazards in NORMA]]<<BR>> [[attachment:mengyuan_slam.pptx |An FPGA-based Real-time Simultaneous Localization and Mapping System]]<<BR>> [[attachment:murray_hetris.pdf |HETRIS: Adaptive Floorplanning for Heterogeneous FPGAs]]<<BR>> [[attachment:rodionov_auto-topo.pptx |Automatic FPGA System and Interconnect Construction with Multicast and Customizable Topology]]<<BR>> [[attachment:shuanglong_mcmc.pdf |An Exact MCMC Accelerator Under Custom Precision]]<<BR>> [[attachment:size_random-tree.pptx |Hardware Design of a Fast, Parallel Random Tree Path Planner]]<<BR>> [[attachment:swathi_behav-hls.pptx |Behavioral-Level IP Integration in High-Level Synthesis]]<<BR>> [[attachment:swathi_jit-trace.pptx |JIT Trace-based Verification in High-Level Synthesis]]<<BR>> [[attachment:wang_fault-soc.pdf |An Adaptive Cross-Layer Fault Recovery Solution for Reconfigurable SoCs]]<<BR>> [[attachment:winterstein_custom-cache.pdf |Custom-Sized Caches in Application-Specific Memory Hierarchies]]<<BR>> [[attachment:yubin_hadoop.pptx |A Self-aware Data Compression System on FPGA in Hadoop]]<<BR>> [[attachment:zhang_cordic.pptx |FPGA Implementation of Low-Power and High-PSNR DCT/IDCT Architecture based on Adaptive Recoding CORDIC]]<<BR>> == Open Reviews (Four best-paper nominations) == [[attachment:review_1.txt|Energy Minimization in the Time-Space Continuum]]<<BR>> [[attachment:review_2.txt|Analyzing the Divide between FPGA Academic and Commercial Results]]<<BR>> [[attachment:review_3.txt|An Adaptive Virtual Overlay for Fast Trigger Insertion for FPGA Debug]]<<BR>> [[attachment:review_4.txt|Accerated Cell Imaging and Classification on FPGAs for Quantitative-phase Asymmetric-detection Time-stretch Optical Microscopy]]<<BR>> <<BR>> |
Keynotes
Andrew Ensor, Technologies for the Square Kilometre Array project
Andre DeHon, Understanding and Exploiting the Energy advantages of Field-Programmable Technologies
Vaughn Betz, The Case for Embedding Networks-on-Chip in FPGA Architectures
Papers
Improved Carry Chain Mapping for the VTR Flow
A Co-Design Approach for Accelerated SQL Query Processing via FPGA-based Data Filtering
Leftmost Longest Regular Expression Matching in Reconfigurable Logic
Packet Processing with a NoC-Enhanced FPGA
Resource and Memory Management Techniques for the High-Level Synthesis of Software Threads into Parallel FPGA Hardware
Exploring Pipe Implementations using an OpenCL Framework for FPGAs
Energy Minimization in the Time-Space Continuum (best paper)
Analyzing the Divide between FPGA Academic and Commercial Results
A Fully Pipelined Kernel Normalised Least Mean Squares Processor For Accelerated Parameter Optimisation
Using Round-Robin Tracepoints to Debug Multithreaded HLS Circuits on FPGAs
Provably Correct Development of Reconfigurable Hardware Designs via Equational Reasoning
Accerated Cell Imaging and Classification on FPGAs for Quantitative-phase Asymmetric-detection Time-stretch Optical Microscopy
QuickDough:A Rapid FPGA Loop Accelerator Design Framework Using Soft CGRA Overlay
OpenCL Library of Stream Memory Components Targeting FPGAs
Braiding: a Scheme for Resolving Hazards in NORMA
An FPGA-based Real-time Simultaneous Localization and Mapping System
HETRIS: Adaptive Floorplanning for Heterogeneous FPGAs
Automatic FPGA System and Interconnect Construction with Multicast and Customizable Topology
An Exact MCMC Accelerator Under Custom Precision
Hardware Design of a Fast, Parallel Random Tree Path Planner
Behavioral-Level IP Integration in High-Level Synthesis
JIT Trace-based Verification in High-Level Synthesis
An Adaptive Cross-Layer Fault Recovery Solution for Reconfigurable SoCs
Custom-Sized Caches in Application-Specific Memory Hierarchies
A Self-aware Data Compression System on FPGA in Hadoop
FPGA Implementation of Low-Power and High-PSNR DCT/IDCT Architecture based on Adaptive Recoding CORDIC
Open Reviews (Four best-paper nominations)
Energy Minimization in the Time-Space Continuum
Analyzing the Divide between FPGA Academic and Commercial Results
An Adaptive Virtual Overlay for Fast Trigger Insertion for FPGA Debug
Accerated Cell Imaging and Classification on FPGAs for Quantitative-phase Asymmetric-detection Time-stretch Optical Microscopy