== Keynotes ==
[[attachment:ensor_keynote.pdf|Andrew Ensor, Technologies for the Square Kilometre Array project]]<
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[[attachment:dehon_keynote.pdf|Andre DeHon, Understanding and Exploiting the Energy advantages of Field-Programmable Technologies]]<
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[[attachment:betz_keynote.pptx|Vaughn Betz, The Case for Embedding Networks-on-Chip in FPGA Architectures]]<
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== Papers ==
[[attachment:ana_carry-chain-vtr.pptx |Improved Carry Chain Mapping for the VTR Flow]]<
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[[attachment:andreas_sql.pdf |A Co-Design Approach for Accelerated SQL Query Processing via FPGA-based Data Filtering]]<
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[[attachment:atasu_leftmost-regex.pdf |Leftmost Longest Regular Expression Matching in Reconfigurable Logic]]<
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[[attachment:bitar_pp-noc.pptx |Packet Processing with a NoC-Enhanced FPGA]]<
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[[attachment:choi_hls-threads.pdf |Resource and Memory Management Techniques for the High-Level Synthesis of Software Threads into Parallel FPGA Hardware]]<
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[[attachment:chow_opencl-pipes.pdf |Exploring Pipe Implementations using an OpenCL Framework for FPGAs]]<
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[[attachment:dehon_space-time.pdf |Energy Minimization in the Time-Space Continuum]] ('''best paper''')<
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[[attachment:elias_commercial-vs-academic.pdf|Analyzing the Divide between FPGA Academic and Commercial Results]]<
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[[attachment:fraser_knlms.pdf |A Fully Pipelined Kernel Normalised Least Mean Squares Processor For Accelerated Parameter Optimisation]]<
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[[attachment:goeders_debug-hls.pdf |Using Round-Robin Tracepoints to Debug Multithreaded HLS Circuits on FPGAs]]<
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[[attachment:harrison_eqnreason.pdf |Provably Correct Development of Reconfigurable Hardware Designs via Equational Reasoning]]<
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[[attachment:hayden_cell.pdf |Accerated Cell Imaging and Classification on FPGAs for Quantitative-phase Asymmetric-detection Time-stretch Optical Microscopy]]<
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[[attachment:hayden_quickdough.pdf |QuickDough:A Rapid FPGA Loop Accelerator Design Framework Using Soft CGRA Overlay]]<
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[[attachment:jasmina_opencl-streams.pdf |OpenCL Library of Stream Memory Components Targeting FPGAs]]<
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[[attachment:leong_braiding.pdf |Braiding: a Scheme for Resolving Hazards in NORMA]]<
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[[attachment:mengyuan_slam.pptx |An FPGA-based Real-time Simultaneous Localization and Mapping System]]<
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[[attachment:murray_hetris.pdf |HETRIS: Adaptive Floorplanning for Heterogeneous FPGAs]]<
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[[attachment:rodionov_auto-topo.pptx |Automatic FPGA System and Interconnect Construction with Multicast and Customizable Topology]]<
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[[attachment:shuanglong_mcmc.pdf |An Exact MCMC Accelerator Under Custom Precision]]<
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[[attachment:size_random-tree.pptx |Hardware Design of a Fast, Parallel Random Tree Path Planner]]<
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[[attachment:swathi_behav-hls.pptx |Behavioral-Level IP Integration in High-Level Synthesis]]<
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[[attachment:swathi_jit-trace.pptx |JIT Trace-based Verification in High-Level Synthesis]]<
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[[attachment:wang_fault-soc.pdf |An Adaptive Cross-Layer Fault Recovery Solution for Reconfigurable SoCs]]<
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[[attachment:winterstein_custom-cache.pdf |Custom-Sized Caches in Application-Specific Memory Hierarchies]]<
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[[attachment:yubin_hadoop.pptx |A Self-aware Data Compression System on FPGA in Hadoop]]<
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[[attachment:zhang_cordic.pptx |FPGA Implementation of Low-Power and High-PSNR DCT/IDCT Architecture based on Adaptive Recoding CORDIC]]<
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== Open Reviews (Four best-paper nominations) ==
[[attachment:review_1.txt|Energy Minimization in the Time-Space Continuum]]<
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[[attachment:review_2.txt|Analyzing the Divide between FPGA Academic and Commercial Results]]<
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[[attachment:review_3.txt|An Adaptive Virtual Overlay for Fast Trigger Insertion for FPGA Debug]]<
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[[attachment:review_4.txt|Accerated Cell Imaging and Classification on FPGAs for Quantitative-phase Asymmetric-detection Time-stretch Optical Microscopy]]<
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