Improved Carry Chain Mapping for the VTR Flow
[[attachment:andreas_sql.pdf |A Co-Design Approach for Accelerated SQL Query Processing via FPGA- based Data Filtering]]
[[attachment:atasu_leftmost-regex.pdf |Leftmost Longest Regular Expression Matching in Reconfigurable Logi c]]
Packet Processing with a NoC-Enhanced FPGA
[[attachment:choi_hls-threads.pdf |Resource and Memory Management Techniques for the High-Level Synthe sis of Software Threads into Parallel FPGA Hardware]]
[[attachment:chow_opencl-pipes.pdf |Exploring Pipe Implementations using an OpenCL Framework for FPGAs] ]
Energy Minimization in the Time-Space Continuum
Analyzing the Divide between FPGA Academic and Commercial Results
[[attachment:fraser_knlms.pdf |A Fully Pipelined Kernel Normalised Least Mean Squares Processor Fo r Accelerated Parameter Optimisation]]
[[attachment:goeders_debug-hls.pdf |Using Round-Robin Tracepoints to Debug Multithreaded HLS Circuits o n FPGAs]]
[[attachment:harrison_eqnreason.pdf |Provably Correct Development of Reconfigurable Hardware Designs via

[[attachment:hayden_cell.pdf |Accerated Cell Imaging and Classification on FPGAs for Quantitative -phase Asymmetric-detection Time-stretch Optical Microscopy]]
[[attachment:hayden_quickdough.pdf |QuickDough:A Rapid FPGA Loop Accelerator Design Framework Using Sof t CGRA Overlay]]
OpenCL Library of Stream Memory Components Targeting FPGAs
Braiding: a Scheme for Resolving Hazards in NORMA
[[attachment:mengyuan_slam.pptx |An FPGA-based Real-time Simultaneous Localization and Mapping Syste m]]
HETRIS: Adaptive Floorplanning for Heterogeneous FPGAs
[[attachment:rodionov_auto-topo.pptx |Automatic FPGA System and Interconnect Construction with Multicast and Customizable Topology]]
An Exact MCMC Accelerator Under Custom Precision
Hardware Design of a Fast, Parallel Random Tree Path Planner<<BR> > Behavioral-Level IP Integration in High-Level Synthesis
JIT Trace-based Verification in High-Level Synthesis
[[attachment:wang_fault-soc.pdf |An Adaptive Cross-Layer Fault Recovery Solution for Reconfigurable SoCs]]
Custom-Sized Caches in Application-Specific Memory Hierarchies<<B R>> A Self-aware Data Compression System on FPGA in Hadoop
[[attachment:zhang_cordic.pptx |FPGA Implementation of Low-Power and High-PSNR DCT/IDCT Architectur e based on Adaptive Recoding CORDIC]]